The present invention is related to a new metallization structure being part of a structure used to interconnect electronic components or devices. Such components or devices can be part of an integrated circuit. Particularly, a multi-level Cu-containing metallization structure is disclosed based on fluorine-containing dielectrics.
The ongoing miniaturization in integrated circuits with increased complexity and multilevel metal layers and the focus on increasing speed of these circuits demand for low permittivity materials, particularly for use as intermetal dielectric layers. Conventionally, metal interconnects, mostly aluminum layers, with silicon dioxide as intermetal dielectric are used, but this conventional solution will not be able to meet the stringent specifications resulting from the above mentioned trends. Therefore, to avoid that the larger portion of the total circuit delay is caused by the resistance and capacitance of the interconnect system, one has to reduce the permittivity of the dielectric used. This is stated in numerous publications, e.g. in Table 1 of R. K. Laxman, xe2x80x9cLow xcex5 dielectric: CVD Fluorinated Silicon Dioxidesxe2x80x9d, Semiconductor International, May 1995, pp. 71-74. Therefore miniaturization has lead to an intensified search for new low K materials. A low xcex5 material, a low K material and a material with a low permittivity are all alternative expressions for a material with a low dielectric constant, at least for the purposes of this disclosure. The most desirable material should have a low K value, low mechanical stress, high thermal stability and low moisture absorption. Furthermore, the desired material should be selected based on the compatibility with state-of-the-art semiconductor processing steps and tools.
Part of the search for new low K materials was directed to changing the properties of silicon dioxide as deposited. Deposited silicon dioxide is the most widely used intermetal dielectric material having a K value of about 3.9. Several publications have indicated that the K value of silicon dioxide films can be reduced by introducing increasing amounts of fluorine in said films. Fluorine is the most electronegative and the least polarizable element on the periodic table. Incorporation of fluorine reduces the number of polarizable Si-OH bonds and also influences the silicon oxide such that it has a less polarizable geometry to thereby lowering the K value of the fluorinated silicon oxide films. A wide variety of processes to deposit fluorinated silicon oxide films are known like e.g. a Plasma Enhanced Chemical Vapour Deposition (PECVD) process as in the U.S. Pat. No. 5,641,581. Using these processes K values in the range between 3 and 3.5 are reported dependent on the amount of fluorine atoms incorporated, i.e. an increasing amount of fluorine leads to a decrease of the K value.
Besides the focus on changing the properties of silicon oxide, there is an ongoing search for new low K materials. Among these new materials are the organic spin-on materials, having a K value in the range from 2.5 to 3, and the inorganic low-K materials as e.g. xerogels having a K value typically lower than 1.5. Many of these new low-K materials comprise fluorine. The organic materials are of particular interest because they feature simplified processing, excellent gap-fill and planarization. Furthermore the K-value of organic materials, which comprise Phenyl groups, can be additionally lowered by plasma fluorination as e.g. in H. Kudo et al., Mat. Res. Symp. Proc., Vol. 381, pp. 105-110, 1985. By doing so the K-values can be lowered yielding a range from 2 to 2.5 instead of from 2.5 to 3.
In summary, it is clear that fluorine-containing dielectrics have in general a lower K-value than there unfluorinated counterparts. This holds both for polymer like and ceramic like dielectrics. Therefore fluorine-containing dielectrics are of particular interest in order to avoid that the larger portion of the total circuit delay is caused by the capacitance of the interconnect system. Despite all these advantages fluorine-containing dielectrics are not compatible with current metallization structures using metallization materials such as Ti, or Ta, or W, or the nitrides of each of the aforementioned materials, or Cu, or Al. This is due to the fact that the incorporation of fluorine has been shown to be detrimental for the aforementioned metallization materials.
It is an aim of the present invention to provide a metallization structure which is compatible with fluorine-containing dielectrics. Therefore, a layer has to be provided which is at least conductive and substantially impermeable for fluorine, i.e. forms a diffusion barrier for fluorine. Preferably, this layer has a low contact resistance to a silicon layer or silicon substrate. In case this metallization structure comprises Cu, a layer has to be provided which is substantially impermeable for Cu.
It is a further aim of the invention to provide a metallization structure being compatible with fluorine-containing dielectrics and comprising a layer which is at least conductive, impermeable for fluorine and impermeable for Cu. Even more preferably, this layer has a low contact resistance to a silicon layer or silicon substrate.
In an aspect of the invention a metallization structure is disclosed comprising a barrier layer, said barrier layer being formed on the exposed parts, i.e. the uncovered parts, of a fluorine-containing dielectric. This barrier layer should adhere well on said fluorine-containing dielectric. This barrier layer should also neither corrode nor reveal a deterioration of its characteristics by the exposure to a fluorine. Furthermore, this barrier layer should also form a diffusion barrier for fluorine, by forming stable non-volatile fluorides, in order to inhibit the corrosion of other parts of the metallization structure. According to this aspect of the invention, a metallization structure is disclosed comprising:
a conductive pattern;
a fluorine-containing dielectric; and
a barrier layer comprising at least a first part, being positioned between said fluorine-containing dielectric and said conductive pattern, said first part consisting of a first sub-layer of a conductive material and a second sub-layer of a fluoride of said conductive material adjacent to said fluorine-containing dielectric. Particularly both the conductive pattern and the fluorine-containing dielectric can be completely encapsulated by the barrier layer.
In an embodiment of the invention, a metallization structure is disclosed comprising a barrier layer of a near noble metal which is at least highly impermeable for fluorine and preferably impermeable for Cu. Preferably the near noble metal Co is use which forms a barrier layer which is both substantially impermeable for fluorine and for Cu. Co is much less reactive than the refractory metals. Co adheres well on fluorine-containing silicon oxide based materials as well as on fluorine-containing organic polymers. Moreover, in contact with a silicon substrate Co can form a silicide-cobalt having a low resistivity and a low contact resistance to a silicon substrate. For the purposes of this disclosure, a silicide-cobalt is defined as CoxSiy, x and y being positive numbers. Moreover, the fluorides of Co are stable and non-volatile, i.e. contrary to e.g. Ti. Furthermore, it has been revealed that Co reacts readily with fluorine thereby forming an in-situ cobalt-fluoride layer, i.e. a layer of CoxFy, x and y being positive numbers. The growth of this cobalt-fluoride layer is self limiting resulting in a maximum thickness of the layer of about 5 nm. The thickness of this layer is typically 3 to 4 nm. Consequently, contrary to e.g. Ti which is permeable for fluorine, by the reaction of Co or another near noble metal, such as Ni, Pd or Pt, with a fluorine-containing dielectric a layer of a fluoride of this near noble metal is formed. This layer inhibits the out-diffusion of fluorine from said fluorine-containing dielectric and thereby avoids the exposure of other parts of the metallization structure to fluorine.
In another embodiment of the invention, a metallization structure is disclosed where the conductive pattern is composed of at least one metal selected from a group comprising Al, Cu, an Al-alloy and a Cu-alloy. Particularly, a Cu-containing metals is selected. This metallization structure can further comprise a barrier layer, impermeable for copper, being positioned between said conductive pattern and said contact barrier layer. Preferably, this barrier layer is a Ta layer or a compound thereof.
In another embodiment of the invention, a metallization structure is disclosed, further comprising a second part of said barrier layer of said conductive material, being positioned between silicon layer and said conductive pattern and wherein said second part is in contact with said silicon layer. Particularly, the silicon layer can be at least a part of a silicon wafer. This second part of said barrier layer comprises a first sub-layer of said conductive material, e.g. Co or another near noble material, and a second sublayer of a silicide of said conductive material, e.g. a silicide-cobalt, said second sub-layer contacting said silicon layer. This second sub-layer provides a low ohmic contact to the exposed parts of the silicon layer.
In another aspect of the invention, a method for fabricating a metallization structure on a substrate is disclosed, comprising the steps of:
depositing a layer of a conductive material on at least one exposed surface of a fluorine-containing dielectric formed on said substrate;
allowing the reaction between said layer of said conductive material and said fluorine-containing dielectric to thereby form a layer of a fluoride of said conductive material at the interface between said layer of said conductive material and said fluorine-containing dielectric; and
depositing at least one metal on said layer of said conductive material. depositing a contact barrier layer on a patterned fluorine-containing dielectric layer thereby creating a diffusion barrier for fluorine; and
forming a conductive pattern on said first contact barrier.
In a further embodiment of the present invention the reaction between the layer of the conductive material, i.e. the barrier layer, and the fluorine-containing dielectric is stimulated by heating the substrate. Particularly, this heating can be performed at a temperature between room temperature and 500 degrees C., or between 50 degrees C. and 500 degrees C., or between 50 degrees C. and 300 degrees C.
In another embodiment of the invention, a method is disclosed to fabricate a metallization structure, wherein prior to the formation of the conductive pattern, preferably composed of Cu or a Cu-alloy, an additional layer, impermeable for Cu, is deposited on the barrier layer of the near noble metal. Preferably, this additional layer is a layer comprising Ta or a compound thereof.